Various key technologies have been developed for bonding wafers or wafer surfaces and are now sufficiently known in the prior art. These include: aligned wafer bonding; front-to-backside photolithography; and customized resist coating.
The present invention primarily relates to aligned wafer bonding in which various methods can in turn be used. These are also described comprehensively in the literature. They include among others: anodic/electrostatic bonding of silicon on glass; low-temperature glass frit bonding of silicon on silicon; and direct wafer bonding (DWB) or fusion bonding.
Further methods are eutectic bonding, epoxy bonding, thermo-compression bonding and glass-on-glass bonding.
In this case, the methods described in the prior art for aligned wafer bonding always consist of the following two separate and different steps. The two wafers arranged one above the other are first aligned with the aid of an alignment device with an accuracy of +/−1 μm, wherein the surfaces of the two wafers which are to be bonded, lie opposite to one another. In this first step it is necessary to maintain a separation distance between the two surfaces to be bonded. In the prior art this is mostly accomplished by spacers which are distributed on the circumferences of the wafers, with the smallest possible surface being covered by these. However, in order to ensure a stable hold, at least three such spacers are required.
The two wafers are then placed under vacuum in a vacuum chamber after which the two previously aligned wafers are brought in contact by means of a computer control system and are joined or bonded by one of the methods described above. For contacting the spacers arranged on the circumferences are withdrawn uniformly so that the previously aligned spacers do not slip any more.
The hitherto known methods for aligned wafer bonding consequently have two important disadvantages. Firstly, gaps are formed by the spacers in the contact surface and on the other hand, during contacting by withdrawing the spacers there is the risk that the wafers which have previously been positioned exactly, slip relative to one another.